1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device. More specifically, the invention relates to a planarization technology in a semiconductor integrated circuit device.
2. Description of the Related Art
On a semiconductor substrate various elements, such as isolation layer, a stacked capacitor, metal wiring and so forth, are formed to form a large step. When a photolithographic method in a condition where the step is maintained, the focusing margin becomes small to cause lowering of pattern precision. Furthermore, due to decreasing of step coverage of a deposited metal layer, breakage of wiring can be caused easily. Therefore, in the prior art, various surface planarization technologies, such as glass flowing method, SOG Spin on Glassy method, etching back method, CMP (Chemical Mechanical Polishing) method and so forth, are implemented. Among these methods, attention has been attracted to the CMP method for the capability of obtaining global flatness.
FIGS. 3A to 3C are sections showing planarization technology disclosed in D. Webb, et al., "Complete Intermetal Planarization Using ECR Oxide and Chemical Mechanical Polish" 1992, VMIC Conference Proceeding, pp. 141-148
As show in FIG. 3A, an aluminum wiring 3 is formed on al semiconductor substrate 1 via a silicon oxide layer 2. Next, as show in FIG. 3B, a silicon oxide to be an interlayer insulation film 31 is deposited by an ECR system CVD (Chemical Vapor Deposition) method. Subsequently, as shown in FIG. 3C, the surface is planarized by polishing with the CMP method thereinafter referred to as "first prior art").
On the other hand, Japanese Unexamined Patent Publication (Kokai) No. Heisei 3-295239 proposes a method in which the SOG technology and polishing method are employed in combination as shown in FIGS. 4A to 4C (hereinafter referred to as "second prior art).
At first, as show in FIG. 4A, the aluminum wiring 3 is formed in a layer thickness of 1 .mu.m on the semiconductor substrate 1 via the silicon oxide layer 2. A PSG layer 41 to be the interlayer insulation film is deposited in the thickness of 0.8 .mu.m thereover.
Next, as shown in FIG. 4B, a SOG layer 42 to be a buried layer is spin coated. Then, heat treatment is performed at a temperature of 400.degree. to 450.degree. C. for 30 minutes. Subsequently, as shown in FIG. 4C, polishing of the surface is performed employing hydrofluoric acid of 0.5 to 1.0% for planarization. At this time, by adjusting water content in the SOG layer, polishing speed of the SOG layer is set higher than polishing speed of the PSG layer.
In the first prior art, since the interlayer insulation film is formed by one kind of material, when a region formed as a wide wiring to be a projecting portion (hereinafter referred to as "wide area firing region") is polished, a flat portion is also polished simultaneously. Therefore, when polishing is continued, an absolute "step" 32 remains as shown in FIG. 3C, that makes it difficult to obtain global flatness.
On the other hand, in the second prior art, if polishing is initiated from the condition shown in FIG. 4B, polishing in the wide area wiring region that is as the projecting portion is progressed earlier, so that the SOG on the wire wiring is polished out earlier. Subsequently, the SOG is polished in the flat portion (wiring concentrated portion) and the PSG is polished in the wide area wiring region. However, since the polishing speed of the SOG is higher than that of the PSG, the SOG is polished out except for the recessed portion. This condition is similar to the polishing condition of the first prior art. Therefore, even when polishing is continued in this condition, the absolute step cannot be eliminated.